1. Field of the Invention
The present invention relates to methods for manufacturing complementary metal oxide semiconductor (CMOS) transistors, and more particularly, to methods for manufacturing CMOS transistors with selective epitaxial growth (SEG).
2. Description of the Prior Art
As semiconductor processes advance to very deep sub-micron geometries and with the progress of device miniaturization, enhancing carrier mobility and a driving current of a MOS transistor has become a critical issue. For example, manufacturing source/drain of a MOS transistor with selective epitaxial growth (SEG) technology is used to improve electrical performance of those elements. SEG technology is widely applied in manufacturing numerous kinds of semiconductor devices, such as MOS transistors having raised source/drain region which benefits from good short channel character and low parasitical resistance and a MOS transistor having recessed source/drain which improves drain induced barrier lowering (DIBL) and punchthrough effect and reduces off-state current leakage and power consumption.
Please refer to FIGS. 1-4, which are schematic drawings illustrating a conventional method for manufacturing CMOS transistors. As shown in FIG. 1, a substrate comprising a N-type well 102, a P-type well 104 and a shallow trench isolation (STI) 106 formed in between is provided. A dielectric layer and a polysilicon layer are sequentially formed on the substrate 100 (not shown). Then, a patterned hard mask layer 110 is formed on the substrate 100 and used as an etching mask. Then the polysilicon layer and the dielectric layer are etched to form gate structures 112 and 114 respectively on the N-type well 102 and the P-type well 104.
Please refer to FIG. 1 again. Next, a mask (not shown) is used in an ion implantation process to form P-type lightly doped drains (LDDs) 122 in the N-type well 102 at two sides of the gate structure 112. And another mask (not shown) is used in an ion implantation process to form N-type LDDs 124 in the P-type well 104 at two sides of the gate structure 114. Then, a spacer 126 is formed at sidewall of each gate structure 112 and 114. The spacer 126, the hard mask layer 110, and a mask covering the N-type well 102 (now shown) are used as an implantation mask in an ion implantation process to form a N-type source/drain 144 in the P-type well 104 at two sides of the gate structure 114.
Please refer to FIGS. 2-3. Next, a cap layer 130 covering the P-type well 104 is formed on the substrate 100. As shown in FIG. 3, the cap layer 130, the hard mask layer 110, and the spacer 126 are used as a mask in an etching process to form recesses 140 in the N-type well 102 respectively at two sides of the gate structure 112.
Please refer to FIG. 4. A selective epitaxial growth (SEG) process is performed to form epitaxial silicon layers 142 respectively in each recess 140. The epitaxial silicon layer 142 comprises silicon or silicon germanium (SiGe). It is well known to those skilled in the art that an ion implantation process is performed before forming the recesses 140 or after forming the epitaxial silicon layer 142 with the cap layer 130, the hard mask layer 110, and the spacer 126 being an implantation mask, thus the epitaxial silicon layer 142 can be a source/drain. To improve Ohmic contact between the gate structures 112 and 114 and the contact plugs formed afterwards, the cap layer 130 and the hard mask layer 110 are entirely removed, then a self-aligned silicide (salicide) process is performed to form silicide layers atop of the gate structures 112 and 114, and the source/drains 142 and 144.
Please refer to FIG. 4 again. In case of undesired epitaxial silicon layer formed on the exposed gate structure 112 due to exceeding consumption of the hard mask layer 110 in the etching process, the hard mask layer 110 used in SEG method is made thicker. It is noteworthy that while the hard mask layer 110 covering the gate structure 112 is getting thinner due to consumption in the etching process, the hard mask layer 110 covering the gate structure 114 is protected from consumption by the cap layer 130. Additionally, such consumption happens not only in the etching process, but also in a cleaning process after recess 140 etching, a cleaning process before SEG process, etc. Consequently, there will be a thickness deviation of about 400-500 angstroms between the hard mask layer 110 covering the gate structure 114 and the hard mask layer 110 covering the gate structure 112.
Please refer to FIGS. 5-6, which are scanning electron microscopy (SEM) pictures of a PMOS and an NMOS, respectively. As shown in FIGS. 5 and 6, because of the thickness deviation between the PMOS and the NMOS, the profile of the gate structure 112 is damaged and liner oxide of the spacers 126 is consumed when the hard mask layer 110 covering the gate structures 112 and 114 and the cap layer 130 have to be removed completely. Exceeding consumption of the liner oxide of the spacer 126 even makes the spacer 126 peeled off. Such consumption also happens to the STI 106, therefore the silicide layers may form under the STI 106 and cause current leakage.